The present invention relates to vertical synchronization separation circuits which are used in a television (TV) receiver or the like for generating a vertical output pulse based on a complex synchronization signal extracted from an input image signal. More particularly, this invention relates to a vertical synchronization separation circuit which is capable of eliminating a curve on a TV screen by the generation of an appropriate vertical output pulse even in the case where a complex synchronization signal added to a copy guard signal is input.
Conventionally, a double AFC (Auto Frequency Control) circuit is used to allow a horizontal synchronization signal to coincide with a TV screen output in the TV receiver. FIG. 7 is a block diagram showing an outline structure of the double AFC circuit. A VCO (Voltage Controlled Oscillator) 101 of a double AFC circuit 100 shown in FIG. 7 oscillates at n times the frequency of the horizontal synchronization signal SH, and this output is input into a frequency divider 102. The frequency divider 102 divides the frequency of the output of the VCO 101 in a cycle of the horizontal synchronization signal SH, and at the same time, generates a signal required for allowing the output of the VCO 101 to coincide with the horizontal synchronization signal SH, and outputs this generated signal to a phase comparator 103. The phase comparator 103 compares the phase of the horizontal synchronization signal SH with the phase of the output of the frequency divider 102, and feeds back and outputs an error voltage corresponding to this phase difference in the result of this comparison to the VCO 101. Consequently, a first feed back loop system R1 is formed with the VCO 101, frequency divider 102, and phase comparator 103. With this first feed back loop system R1, the oscillation frequency of the VCO 101 is locked to the horizontal synchronization signal SH in a definite phase relation. This first feed back loop system R1 generates a horizontal output pulse and stops its operation for the period when the vertical output pulse is output.
On the other hand, the frequency divider 102 further generates a signal which is required for comparing the phase of the output from the frequency divider 102 with the phase of a fly back pulse FP output from a fly back transformer 106, and outputs the generated signal to a phase comparator 105. The phase comparator 105 compares the phase of the output from the frequency divider 102 with the phase of the fly back pulse FP, and outputs an error voltage corresponding to the phase difference in the result of this comparison to the horizontal output phase control circuit 104. The horizontal output phase control circuit 104 generates a horizontal output pulse PH required for preparing the fly back pulse FP, and outputs it to a fly back transformer 106. As described above, the fly back transformer 106 generates the fly back pulse FP, and outputs it FP to the phase comparator 105. Consequently, a second feed back loop system R2 is formed with these phase comparator 105, horizontal output phase control circuit 104, and fly back transformer 106. This second fly back loop system R2 allows the horizontal synchronization signal SH to coincide with the TV screen output. The fly back transformer 106 generates each kind of voltage which is synchronized with the horizontal synchronization signal SH, and also generates a voltage corresponding to the TV screen output. A part of the voltage is then flied back and output to the phase comparator 105 as a fly back pulse FP.
The horizontal synchronization signal SH which is input to this double AFC circuit 100 is output from a synchronizing separation section 110. FIG. 8 is a block diagram showing an outline structure of the synchronizing separation section 110. As shown in FIG. 8, the synchronization separation section 110 outputs the horizontal synchronization signal SH and the vertical output pulse PV from the input image signal S1. The synchronization separation section 110 comprises a synchronization separation circuit 111, a horizontal synchronization separation circuit 112, and a vertical synchronization separation circuit 113. The synchronization separation circuit 111 separates a complex synchronization signal SC in which the horizontal synchronization signal and the vertical synchronization signal exist together from the input image signal S1 and outputs the complex synchronization signal SC to the horizontal synchronization separation circuit 112 and the vertical synchronization separation circuit 113.
The horizontal synchronization separation circuit 112 outputs the horizontal synchronization signal SH, by which an equivalent pulse and a vertical synchronization signal are extracted from the complex synchronization signal SC, to the double AFC circuit 100. On the other hand, the vertical synchronization circuit 113 separates only the vertical synchronization signal from the complex synchronization signal SC and outputs it as a vertical output pulse PV. The operation of the double AFC circuit 100 is suspended if the vertical output pulse PV is output.
FIG. 9 is a circuit diagram showing a detailed structure of the vertical synchronization circuit 113. As shown in FIG. 9, this vertical synchronization separation circuit 113 has a first comparator 11 in which transistors TR1 and TR2 are operated as a differential pair. The first comparator 11 compares the complex synchronization signal SC input from an input terminal T1 with the first reference voltage V1. The input terminal T1 is connected to the base of the transistor TR1 while the positive side of the first reference voltage V1 is connected to the base of the transistor TR2. The power source 1 and the capacitor C1 are connected to a terminal T11 on the collector side of the transistor TR2. The other end of the capacitor C1 is grounded. The other end of the current source 1 and the collector of the transistor TR1 are connected to the power source Vcc. The emitters of the transistors TR1 and TR2 are connected commonly with the power source 3, and grounded. Furthermore, the value of the current I3 which the current source 3 outputs is set to a value larger than the current I1 which the current source 1 outputs.
Consequently, when the first reference voltage V1 is larger than the voltage of the complex synchronization signal SC, an electric load accumulated in the capacitor C1 is discharged because current I3 is larger than current I1. When the first reference voltage V1 is lower than the voltage of the complex synchronization signal SC, the capacitor C1 is charged with the current I1 supplied by the current source 1. Therefore, the voltage Vc that is obtained by the integration of the complex synchronization signal SC is generated in the capacitor C1.
The voltage Vc of this capacitor C1 is applied to the base of the transistor TR3 out of the transistors TR3 and TR4 as differential pairs which constitute the second comparator 12. Furthermore, the second reference voltage V2 is applied to the base of the transistor TR4, and the second comparator 12 compares the voltage Vc and the second reference voltage V2. The collector of the transistor TR3 is connected to the power source Vcc, and the collector of the transistor TR4 is connected to the power source Vcc via a resistor R1. From a connection between the collector of the transistor TR4 and the resistor R1, a vertical output pulse PV is output as a comparison result. Furthermore, the emitters of the transistor TR3 and TR4 are connected commonly with the current source 4, and grounded. Operation of the vertical synchronization separation circuit 113 will be explained by referring to a timing chart shown in FIG. 10A to FIG. 10C. FIG. 10A shows a relation between the complex synchronization signal SC input to the input terminal T1 and the first reference voltage V1. Incidentally, the complex synchronization signal SC shown in FIG. 10A shows a front part of the field. In one field, the complex synchronization signal SC is formed in an order of the equivalent pulse P10 to the vertical synchronization signal SV to the equivalent pulse P11 to the horizontal synchronization signal SH. The complex synchronization signal SC is pulse waveform to assume a negative side (set in a Lo state) to be ON state. In the complex synchronization signal SC, only the vertical synchronization signal SV becomes a wide pulse, compared with the pulse width of other equivalent pulses P10, P11 and horizontal synchronization signal SH.
As a result, as shown in FIG. 10B, the voltage Vc of the capacitor C1 abruptly lowers upon the input of the vertical synchronization signal SV, and becomes smaller than the second reference value V2. Consequently, the vertical output pulse PV is turned on, and the result of the comparison by the second comparator 12 is output for a period during when the vertical synchronization signal SV is input as shown in FIG. 10C. In such a process, the vertical output pulse PV is such that the negative side (Lo) thereof is turned on.
By the way, as shown in FIG. 11A to FIG. 11C, there is a case in which a copy guard signal CG, which is a front part of the vertical synchronization signal SH and is referred to as a micro vision signal during the vertical blanking period, is added to the complex synchronization signal SC. This copy guard signal CG is a signal that is added for preventing a dumping of videotapes. In detail, the copy guard signal CG has a waveform as shown in FIG. 12.
In FIG. 12, one field period, namely the front part of the vertical synchronizing period becomes a twenty-lines section of the vertical blanking period shown by symbols {circumflex over (1)} to {circumflex over (20)}. To each of the lines between the line 13 to line 20, a pseudo-synchronization signal SP and a white level signal SW are added so that the copy guard signal CG is formed. The pseudo-synchronization signal SP has a pulse width of 2 xcexcsec while the white level signal SW has a pulse width of 3.7 xcexcsec. Both the pseudo-synchronization signal and the white level signal are repeated five times in an alternate manner respectively. The signal SY is formed only on line 17 and line 18. Setting to which the copy guard signal CG is added and not added is performed to line 20.
When the complex synchronization signal SC added to such a copy guard signal CG is input to the vertical synchronization separation circuit 113, as shown in FIG. 11C, the vertical synchronizing pulse PV similar to the complex synchronization circuit SC to the copy guard signal CG is not added is output. However, the copy guard signal CG is input together with the horizontal synchronization signal SH into the double AFC circuit 100. Accordingly, the phase comparator 103 generates an error voltage corresponding to a phase difference which is different from a comparison with the horizontal synchronization signal SH in order to compare the phase between the copy guard signal CG and the output of the frequency divider 102. As a result, the oscillation frequency of VCO 101 changes, and the frequency of the horizontal output pulse PH, which is output from the horizontal output phase control circuit 104 which receives an output from the frequency divider 102, changes with the result that a curve is generated on the TV screen. In other words, even when the frequency of the horizontal output pulse PH changes in the vertical blanking period, no curve is generated on the TV screen. However, there arises a problem that since the copy guard signal CG is added to the rear part of the vertical blanking period, the copy guard signal CG is responded to, and a change in the error voltage in the double AFC circuit 100 cannot be converged. Therefore, an output on the TV screen is distorted, and a curve is caused in the upper part of the TV screen.
The present invention has been made in light of the problems described above. It is an object of the present invention to provide a vertical synchronization separation circuit which does not affect the double AFC circuit and which does not generate a curve on the upper part of the TV screen in the case of the separation of the complex synchronization signal to which the copy guard signal is added.
According to a first aspect of the present invention, a switch control unit changes over a first switch to a third current source during a period from the reset of the vertical synchronization up to the termination of the vertical blanking period, and decreases the charge current to the capacitor. Thereby, the detection time of the vertical is quickened, and the vertical output pulse is immediately turned on in the case where the copy guard signal is added to the complex synchronization signal.
Further, the switch control unit generates a control pulse having a timing which covers at least a pulse of the horizontal synchronization signal and a pulse width which is very small as compared to the pulse width of the horizontal synchronization signal in a pulse interval of the horizontal synchronization signal. The switch control unit further carries out a control for turning off a second switch with the control pulse during a period up to the termination of the vertical blanking period.
Other objects and features of this invention will become apparent from the following description with reference to the accompanying drawings.